Computer Organization and Architecture

Input & Output

Outline

• External Devices

• I/O Modules

• Programmed I/O

• Interrupt-Driven I/O

• Direct Memory Access

• I/O Channels and Processors

• The External Interface

External Devices

Input/Output Problems

• Peripherals are used for information exchange between computer and environment

• Wide variety of peripherals

  • Delivering different amounts of data

  • In different formats

  • At different speeds

• Almost all slower than CPU and RAM

• Need I/O modules

  • Connection to processor and memory via system bus or central exchanger

  • Connect with one or more peripherals through a dedicated data line

Function of I/O modules

• Connecting peripherals with system bus

• Not only a connector, but also the communication logic between peripheral devices and system bus

  • many types of peripherals

  • amount of data transmitted varies greatly

  • speed varies greatly

• I/O modules are required to resolve the differences between peripherals and processors

$System\ Bus=Address\ Lines+Data\ Lines+Control\ Lines\newline$

Types of peripherals

• Human readable

  • Screen, printer, keyboard

• Machine readable

  • Monitoring and control

• Communication

  • Modem

  • Network Interface Card (NIC)

• Can also be categorized as

  • Input devices

  • Output devices

  • Input/Output devices

Interface of peripherals

USB interface

Charismatics of USB interface

• Hot plug: Plug and Play

• Portability: Small equipment, easy to carry

• Standard unification: Peripherals can be connected to personal computers with the same interface

• Multiple devices connectivity: More devices can be connected through USB-HUB expansion

External device structure

I/O Modules

Function of I/O module

• Control & Timing

  • Control the operation of peripherals

  • Sequential control

• CPU Communication

  • communication between the processor and peripherals

  • Command decoding, data transmission, status report, address identification

• Device Communication

  • communication with device

  • Command, data and status

• Data Buffering

  • Speed of different peripherals varies greatly

  • Conversion of transmission rate

• Error Detection

Step of data transfer

1. CPU checks I/O module device status

2. I/O module returns status

3. If ready, CPU requests data transfer

4. I/O module gets data from device

5. I/O module transfers data to CPU

Variations for output, DMA

Processor communication

• Command decoding

  • processor sends instructions to the I/O module

  • I/O module decodes the instructions to determine the operations to be completed

• Address recognition

  • Each peripheral has an address, similar to a memory unit

  • Operating instructions include peripheral address

  • I/O module determines which device to operate on according to the address

• Data transfer

  • Data transmission is bidirectional

  • Complete through data bus

• Status reporting

  • Report the status to the CPU to determine whether the current I/O operation is executed

  • Report various error messages

I/O module structure

• Data registers: data buffer to the I/O device

• Status/Control registers

  • Current status

  • or receive control from the processor

  • Connecting to data

• Bus interface: data, address, control

• I/O logic

  • Receive the command sent by the processor

  • Receive address

  • Control peripherals for operation

• External device interface

  • Interact with peripherals

  • Including data, status and control

Three I/O techniques ! ! !

• Programmed I/O

  • The processor executes a program to control the I/O operation

  • The processor needs to wait while I/O processing the command

• Interrupt-driven I/O

  • Processor issues an I/O command, and continues to execute other instructions until the interrupt occurs

• Direct memory access (DMA)

  • The data transfer without processor involvement

Programmed I/O

Interrupt-driven I/O

Direct memory access (DMA)

Programmed I/O

• CPU has direct control over I/O

  • Sensing status

  • Read/write commands

  • Transferring data

• CPU waits for I/O module to complete operation

• Wastes CPU time

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• CPU requests I/O operation

  • I/O module performs operation

  • I/O module sets status bits

• CPU checks status bits periodically

  • I/O module does not inform CPU directly

  • I/O module does not interrupt CPU

• CPU may wait or come back later CPU

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• CPU sends out address

  • Identifies module (& device if >1 per module)

• CPU sends out command

  • Control - telling module what to do

  • Test - check status

  • Read/Write —transfers data via buffer from/to device

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• I/O addressing

  • Typically, there might be many I/O devices connected through I/O modules

  • Each device is given a unique address

  • The I/O instruction contains the address of the desired device

  • Two types of addressing mode are used

    • Memory-mapped I/O

    • Isolated I/O

Memory mapped I/O

I/O mapping - isolated I/O

Interrupt-Driven I/O

• Programmed I/O reduces CPU efficiency

• Interrupt driven I/O overcomes CPU waiting

• No repeated CPU checking of device

• I/O module interrupts when ready

Interrupt processing

• CPU: issues I/O command

• CPU: continues with other tasks

• The module: receives the command and works on the task

• When finished, signals CPU an interrupt

• CPU: checks the interrupt at the end of each instruction cycle

• CPU: if interrupt occurs

  • CPU saves the context

  • Executes interrupt service routine

• CPU: restores the context

• CPU: continues on its primary task

Interrupt processing diagram

CPU viewpoint

• Issue read command

• Do other work

• Check for interrupt at end of each instruction cycle

• If interrupted

  • Save context (registers)

  • Process interrupt

• Restore PSW and PC

Types of device identification

• For device identification, there are four general categories of techniques are in use

  • Multiple interrupt line – each device has a IRQ

  • Software poll

  • Hardware poll (Vectored interrupt)

  • Bus arbitration (Vectored interrupt)

Software poll

• An interrupt service routine polls each I/O module to determine which module caused the interrupt

  • TEST I/O command

  • Status register: After an interrupt is issued by the I/O module, a status register is written. The processor polls this status register

• Once the correct module is identified, the processor branches to a device-service routine specific to that device

• Disadvantage: time consuming

Hardware poll

• All I/O modules share a common interrupt request line

• When the processor senses an interrupt, it sends out an interrupt acknowledge

  • This signal propagates through a series of I/O modules until it gets to a requesting module

  • The requesting module typically responds by placing a word (vector) that identifies the device

  • The processor uses the vector as a pointer to the appropriate device-service routine

• Called vectored interrupt

Bus arbitration

• An I/O module must first gain control of the bus before it can raise the interrupt request line

• When the processor detects the interrupt, it responds on the interrupt acknowledge line

• The requesting module then places its vector on the data line

Multiple interrupts

• FIFO,no priority

• Multiple interrupt line: each interrupt line has a priority

• Hardware poll or software poll: order of polling determines the priority

• Bus arbitration: Arbitration can be conducted in priority mode

Direct Memory Access(DMA)

Why use DMA

• Interrupt driven and programmed I/O require active CPU intervention

  • I/O->processor->memory

  • Transfer rate is limited

  • CPU is tied up

• DMA is the answer

• DMA: Direct Memory Access

  • a module on system bus

  • take over the system control work from the processor

  • transfers data between memory and I/O module

• Both interrupt driven and programmed I/O require the continued involvement of the CPU in the I/O operation

  • $I/O\ device \rightarrow CPU \rightarrow Memory\newline$

  • $I/O\ device \leftarrow CPU \leftarrow Memory\newline$

• DMA takes the CPU out of the task

  • $I/O\ device \rightarrow Memory\newline$
  • $I/O\ device \leftarrow Memory\newline$

DMA function

• Additional Module (hardware) on bus

• DMA controller takes over from CPU for I/O

  • DMA need system bus to complete data transmission

  • It must use the bus only when the processor does not need it

  • Or it must force the CPU to suspend operation temporarily –referred to as cycle stealing! ! !

DMA operation ! ! !

• CPU tells DMA controller

  • Read/Write

  • Device address

  • Starting address of memory block for data

  • Amount of data to be transferred

• CPU carries on with other work

• DMA controller deals with transfer

• DMA controller sends interrupt when finished

• CPU, DMA controller, I/O device exchange the handshake signals

• DMA controller deals with the data transfer

  • I/O device to memory, memory to I/O device

  • Multiple data may be transmitted at one time

• CPU only involved at the beginning and end of the transfer

DMA transfer cycle-stealing ! ! !

• Cycle-stealing: DMA controller takes over bus for a cycle

  • Transfer of one word of data in this cycle

  • Cycle-stealing is not an interrupt

  • CPU does not switch context

• CPU suspended just before it accesses bus

  • i.e. before an operand or data fetch or a data write

• Slows down CPU but not as much as CPU doing transfer

Alternative DMA configurations

• 单总线分离的DMA，DMA、I/O模块和内存都挂在总线上

• DMA是CPU的代理，采用类似于编程式I/O的方式，在内存和I/O之间传送数据

• 每次传送需要消耗2个总线时钟周期。一个周期用于和I/O交换数据，一个周期用于和存储器交换数据

• 配置简单，效率比较低

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• 单总线集成式DMA-I/O结构，I/O模块通过DMA和总线互连

• DMA可能是I/O的一部分，也可能一个DMA控制一个或几个I/O模块

• DMA与I/O之间的数据交换不需要系统总线，只有DMA和存储器交换数据到时候才会用到系统总线，减少了系统总线的开销

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• I/O总线方式，从第二种方式扩充而来

• 在DMA和I/O设备之间配置一条专门的I/O总线

• 可以减少DMA模块的接口数量

• DMA与存储器交换数据的时候才会用到系统总线

Fly-by -1

• DMA and CPU use the bus alternately

• Data does not pass through and is not stored in DMA chip

  • 8237 DMA is known as fly-by DMA controller

  • DMA only between I/O port and memory

  • Not between two I/O ports or two memory locations

• Can perform memory to memory transfer via register

Summary

	Programmed I/O	Interrupt driven I/O	DMA
Operation	CPU checks I/O status repeatedly	I/O device sends request when ready	Data transfer without CPU
Advantage	Simple Polling sequence can be changed by program	Save time	More faster
Disadvantage	Time consuming	Complex	More complex

I/O Channels and Processors

Evolution of I/O function

Peripherals are more and more complex, and I/O functions are also developing

• I/O channel

  • I/O module is enhanced to become a processor(no memory)

  • with a specialized instruction set tailored for I/O

  • The CPU instructs the I/O processor to execute I/O programs in memory

  • Interrupt will not occur until I/O program execution is completed

• I/O processor

  • has a local memory of its own and is, in fact, a computer in its own right

  • Control a large number of I/O devices with minimal CPU participation

  • Controls communication with interactive terminals. The I/O processor handles most of the tasks

Generally, I/O channel and I/O processor are not distinguished. Called as I/O channel

I/O channels operation

• CPU initiates an I/O instruction that instructing the I/O channel to execute a program in memory

• The program will specify the device, the area of memory for storage, priority, error handling

• The I/O channel follows these instructions and controls the data transfer

• I/O channel has two types

  • Selector channel

  • Multiplexor

Selector channel

Multiplexor

The External Interface

Types of interface

Interaction between I/O module & peripherals

• I/O module sends a control signal and requests to send data

• Peripheral responds to the request

• I/O module sends data

• Peripherals acknowledge receipt of data

• Connection type

  • one to one
  • one to many: I/O bus

• Two typical I/O buses: 1394, InfiniBand

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IEEE 1394 FireWire

• High performance serial bus

• Fast

• Low cost

• Easy to implement

• Also being used in digital cameras, VCD and TV

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• Fair arbitration

  • Bus time is divided into equal time intervals

  • During the time interval, each node can request the bus

  • After obtaining bus access, it is not allowed to request the bus again

  • Avoid high priority device exclusive bus

• Urgent arbitration

  • Specific equipment has emergency priority

  • Bus control can be obtained multiple times in the interval

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InfiniBand

• Increased capacity, expandability, flexibility

• Attach servers, remote storage, network devices to central fabric of switches and links

  • Greater server density

  • Scalable data center

  • Independent nodes added as required