Computer Organization and Architecture

Internal Memory

Review

• How Cache works

• Write policy

  • Write through
  • Write back

• Elements of Cache Design

  • Cache Address

  • Cache size

  • Cache mapping

  • Replacement algorithm

  • Write policy

  • Row size

  • number of the caches

• The main method of memory expansion

  • The address space becomes larger(big)

  • The data bus becomes larger(width)

Outline

• Key Terms

• Semiconductor main memory

• Error correction

• Advanced DRAM organization

Key Terms

• cache DRAM (CDRAM)

• dynamic RAM (DRAM)

• electrically erasable programmable (EEPROM)

• ROM (EEPROM)

• erasable programmable ROM(EPROM)

• error correcting code (ECC)

• error correction

• flash memory

• Hamming code

• hard failure

• nonvolatile memory

• programmable ROM(PROM)

• RamBus DRAM (RDRAM)

• read-mostly memory

• read-only memory (ROM)

• semiconductor memory

• single-error-correcting (SEC) code

• single-error-correcting , double-error-detecting (SEC-DED) code

• soft error

• static RAM (SRAM)

• synchronous DRAM (SDRAM)

• Syndrome

• volatile memory

Semiconductor main memory

Core memory

• Memory used earlier,used in the 1950s and 1960s

  • tiny rings of ferromagnetic material

• Characteristics

  • Fast,about 1us
  • Large volume
  • Expensive
  • Volatile,must be written immediately after reading

Semiconductor memory

• Characteristics

  • High storage density

  • Nonvolatile

  • Faster than core, about 70ns

• since 1974, cost continue decreasing, density continue increasing

Semiconductor main memory

• Basic element of memory is cell

  • has two stable states, representing 0 and 1

  • can be changed from 0 to 1, or from 1 to 0

  • can read its current state by some way

• Cell has two operations

  • Read
  • Write

Two basic memory types ! ! !

• RAM – random access memory

  • SRAM - static RAM

  • DRAM - dynamic RAM

• ROM – read only memory

  • ROM

  • PROM – programmable ROM

  • EPROM –Erasable programmable ROM

  • EEPROM – electronically erasable programmable ROM

  • Flash (EEPROM type) Flash

RAM ! ! !

• The most commonly used as main memory

• Can be read and write at any time

• Volatile – must be provided with a constant power supply! ! !

  • When power is on, the content of the RAM cell stays

  • When power is off, the data is gone

• Two major forms of RAM

  • DRAM
  • SRAM

Dynamic RAM

• Use one capacitor to record 1 bit

• Bits stored as charge in capacitors

  • 1: capacitor is charged
  • 0: no electricity in capacitor

• Charge of capacitor leaks automatically

  • Need refreshing even when powered

• Characteristics

  • Simpler construction
  • Smaller per bit

Dynamic RAM structure

DRAM operation

• Address line active when bit read or written

  • Transistor as a switch

• Write

  • Voltage to bit line

    • High for 1 low for 0

  • Then signal address line

    • Transfers charge to capacitor

• Read

  • Address line selected

  • transistor turns on

  • Charge from capacitor fed via bit line to sense amplifier

  • Compares with reference value to determine 0 or 1

  • When reading, the capacitor charges discharge

  • Capacitor charge must be restored

Characteristics of Dynamic RAM

• Less electronic components, high integration and low price

• The charge stored in the capacitor will discharge，refresh circuits needed

• Voltage of the capacitor is an analog value

  • Level of charge determines value

  • Speed of reading and writing is relatively slow Slower

• Main memory

DRAM refresh and row access

• DRAMs MUST be refreshed (rewritten) every 2 to 4ms

• This refresh is performed by a special circuit in the DRAM which refreshes the entire memory

  • Usually accomplished by a “RAS-only” cycle
  • The row address is placed on the address lines and RAS (row address select) asserted. This refreshed the entire row

• CAS (column address select) is not asserted

• Unused data is placed on the external data lines

Loss of Bandwidth to Refresh Cycles

Static RAM

Static RAM structure

Static RAM operation

• Write

• Read

Characteristics of Static RAM

• Advantage

  • No charges to leak

  • No refreshing needed when powered

  • Faster

  • Digital

• Disadvantage

  • More complex construction

  • Larger per bit

  • More expensive

• Used as Cache

SRAM VS DRAM

• Both volatile, Power needed to preserve data

Read only memory(ROM)

• Permanent storage

  • Nonvolatile

• While it is possible to read a ROM, it is not possible to write new data into it

• Important application

  • Microprogramming

  • Library subroutines

  • Systems programs (BIOS)

  • Function tables

Structure of ROM

Types of ROM

• True ROM: written during manufacture

  • Very expensive for small runs

  • ROM

  • Factory programmed, cannot be changed. Older style

  • There is no room for error

  • Programmable (only once)

    • PROM
    • Needs special equipment to program

• Read “mostly”

  • Erasable Programmable (EPROM)

    • Erased by UV

    • Can be written repeatedly for many times

    • More expensive

  • Electrically Erasable (EEPROM)

    • Write directly after locating one or more bytes

    • Takes much longer to write than read

    • More flexible，more expensive

  • Flash memory

    • Block storage

    • Erase whole memory electrically

    • High integration and high storage density

    • Widespread use

Memory organization

• Multiple memory chips form a memory array

  • Some are organized as two dimensional array

  • Some chips are organized as one dimensional array

  • The data is read/written in bits

Memory line access

Memory grid access

Organization in detail

• 1M words, 16bit of each word can be organized in two ways

  • A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1,and so on

  • Two 1M * 8bit chips, the high 8 bits of each word are on one chip, and the low 8 bits are on the other chip

• A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array

  • Reduces number of address pins

  • Multiplex row address and column address

  • 11 pins to address ($2^{11}=2048$)

  • Adding one more pin doubles range of values so x4 capacity(row x2 and column x2)

Typical 16Mb DRAM

Chip packaging

Generic pin configuration

• Besides the address lines and data lines, each memory device has at least one chip select pin that enables the memory device

• Each RAM device has read or write control pin

  • WE: Write Enable

  • OE: Output Enable

2K * 8 EPROM chip

2K * 8 SRAM chip

64K * 4 DRAM chip

Expand memory

Expand memory to be larger

Expand memory to be wider

Memory address decoding

• Address decoding is the process of generating chip select (CS*) signals from the address bus for each device in the system

Two methods of decoding strategy

• Full address decoding

  • All the address lines are used to specify a memory location

  • Each physical memory location is identified by a unique address

• Partial address decoding

  • If only a portion of the addressable space is going to be implemented, then not all the address space is implemented

  • Only a subset of the address lines are needed to point to the physical memory locations

Interleaved memory

• Collection of DRAM chips

• K banks can service k requests simultaneously

• Improve the response speed of the storage system

Error correction

• Hard Failure: Permanent defect

• Soft Error: Random, non-destructive, no permanent damage to memory

• Most modern main memory systems include logic for both detecting and correcting errors

  • Fault tolerance of the system is improved

  • Width of memory word increased(For correcting error)

Error correcting code function

Hamming Error-correcting code! ! !

• How many check bits are needed

$$ n\ information\ bits\ and\ k\ check\ bits\newline n+k+1 \le 2^k\newline $$

Example

信息位:1010

• 确定位数: $2^k \ge n + k + 1\rightarrow k = 3\newline$

• 设信息位为$D_4D_3D_2D_1(1010)$，校验位为$P_3P_2P_1$,对应的Hamming code为$H_7H_6H_5H_4H_3H_2H_1\newline$

  • ! ! !校验位$P_i$放在Hamming code的$H_{2^{i-1}}$的位置上
  • 信息位按照与Hamming code相同单调性的方向放入

• 按照Hamming code分为三组

• 求校验位的值

  • 对于信息位

$$ \begin{align} &H_3: 3 \rightarrow 011\newline &H_5: 5 \rightarrow 101\newline &H_6: 6 \rightarrow 110\newline &H_7: 7 \rightarrow 111\newline \end{align} $$

• 校验位的下标对应的二进制的第几位（权重)
  • $P_1 \rightarrow 二进制的最小一位(权重为1),P_2 \rightarrow 权重为2\newline$
  • 相应的位置(对应权重部分是1，比如$P_1$,在二进制里面只有3,5,7末尾权重唯一的bit处为一，所以计算$H_3,H_5,H_7$)进行异或运算（也就是偶校验）

$$ \begin{align} &P_1=H_3 \oplus H_5 \oplus H_7=0\newline &P_2=H_3 \oplus H_6 \oplus H_7=1\newline &P_3=H_5 \oplus H_6 \oplus H_7=0\newline \end{align} $$

所以得到海明码$1010010\newline$

• 纠错

校验方程 $$ \begin{align} &S_1=P_1\oplus H_3 \oplus H_5 \oplus H_7=P_1 \oplus D_1 \oplus D_2 \oplus D_4\newline &S_2=P_2\oplus H_3 \oplus H_6 \oplus H_7=P_2 \oplus D_1 \oplus D_3 \oplus D_4\newline &S_3=P_3\oplus H_5 \oplus H_6 \oplus H_7=P_3 \oplus D_2 \oplus D_3 \oplus D_4\newline \end{align} $$ 没有出错的情况应该是都等于0

如果为其他结果

$error\ bit \rightarrow H_{S_3S_2S_1 \rightarrow decimal}\newline$

• Example $S_3S_2S_1=010\newline$,则应该是010位出现了错误$H_2(010 \rightarrow 2)\newline$

• $S_3S_2S_1=110,H_6(110\rightarrow 6)\newline$

• 特点

  • 纠错能力 1位
  • 检错能力 2位
  • 加强：在首部加上一个全校验位，对整体进行偶校验
    • $S_3S_2S_1=000$且全体偶校验成功：无错误
    • $S_3S_2S_1 \ne 000$且全体偶校验失败：有1位错误，纠正即可
    • $S_3S_2S_1 \ne 000$且全体偶校验成功：有2位错误，需重传

Summary

• Error correction is to improve its reliability by processing data and increasing its internal correlation

• In memory, SEC-DED （single-error-correcting, double-errordetecting）code is commonly used

• The more data bits processed in a single time, the less space waste

Advanced DRAM organization

• The performance of DRAM seriously affects the performance of the computer

• Many methods are proposed to improve the performance of memory itself

  • SDRAM

  • Rambus DRAM

  • DDR SDRAM

  • Cache DRAM

Synchronous DRAM (SDRAM)

• Access is synchronized with an external clock

• Address is presented to RAM，RAM finds data

  • CPU does not have to wait, it can do something else. (CPU waits in conventional DRAM)

  • Since SDRAM moves data in time with system clock, CPU knows when data will be ready

• Burst mode allows SDRAM to set up stream of data and fire it out in block

RAMBUS DRAM

• Adopted by Intel for Pentium & Itanium

• Main competitor to SDRAM

• Vertical package – all pins on one side

• Data exchange over 28 wires < 12cm long

• Bus addresses up to 320 RDRAM chips at 1.6Gbps

• Asynchronous block protocol

  • 480ns access time

  • Then 1.6 Gbps

Cache DRAM

• Integrates small SRAM cache (16 kb) onto generic DRAM chip

• Used as true cache

  • 64-bit lines

  • Effective for ordinary random access

• To support serial access of block of data

• E.g. refresh bit-mapped screen

  • CDRAM can prefetch data from DRAM into SRAM buffer

  • Subsequent accesses solely to SRAM